This invention relates generally to memory cell arrays, and, more specifically, to techniques of segmenting long conductive lines within the array and operating the array in segments. Although the invention has application to a wide variety of types of memory cell arrays, it is described herein to be implemented in a non-volatile memory, specifically a flash electrically-erasable and programmable read-only memory (flash EEPROM).
Memory cells of one type of array are arranged in a rectangular pattern with an individual cell being addressable by placing appropriate voltages on two perpendicular conductors that cross at the desired cell. These conductors are typically a word line which extends along a row of memory cells, and a bit line that extends along a column of memory cells. A first type of flash EEPROM architecture to be discussed herein uses cells that individually include a floating gate memory transistor and a select transistor in series between adjacent source and drain diffusions. The source and drain diffusions are connected to adjacent bit lines. Each word line is connected to control gates of the memory transistors and to gates of the select transistors of the cells along one row. Examples of the structures of such memory cells, and the architectures of memory arrays using them, are given in the following United States patents, which patents are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,343,063, 5,579,259 and 5,661,053. In these examples, a cell is programmed by injecting electrons onto its floating gate from the channel, and erased by removing electrons from the floating gate to a separate erase gate.
In order to have better control over the reading and programming functions, a second type of this form of memory electrically separates the control gate and the select transistor gate of each cell, connecting the control gates to added steering gate lines which run along columns of memory cells. In this form of memory, the word lines are connected only to the gates of the select transistors. This second type of memory cell is described, for example, in U.S. Pat. No. 5,313,421, which patent is incorporated herein in its entirety by this reference. The floating gates are erased to the word lines.
In order to increase the density of floating gates in the array, a third type of memory cell includes two floating gate transistors and a single select transistor in between them, the three transistors being positioned between adjacent source and drain diffusions. Steering gate lines extend over floating gates in the column direction, and word lines are connected to select transistor gates of memory cells along the rows. This type of cell is described in U.S. Pat. No. 5,712,180 (particularly FIGS. 9A through 10C thereof), U.S. Pat. Nos. 6,103,573 and 6,151,248, and pending application Ser. No. 09/667,344, filed Sep. 22, 2000, which patents and application are incorporated herein in their entirety by this reference.
In order to improve the performance of a large memory array, an array of one of the types identified above is typically segmented into smaller portions or sub-arrays in the direction of the columns. U.S. Pat. No. 5,315,541, which is incorporated herein in its entirety, divides the bit lines of a memory array of the first type identified above into electrically localized segments. The bit lines of each segment are connectable to global bit lines through segment-select transistors. FIG. 10C of aforementioned U.S. Pat. No. 5,712,180 and its accompanying text, describes a segmentation of the third type of memory identified above wherein both the columnar extending bit lines and steering gates are divided into equal segments. A primary motivation for segmenting a memory is to reduce the resistance and capacitance of a line whose voltage needs to be changed rapidly. This need has increased as the arrays have been made larger and more dense, and as the operating speeds have increased.
According to one aspect of the present invention, a memory array, such as the second or third type identified above, has both its steering gate lines and bit lines segmented in a columnar direction but the steering gate lines are divided into longer segments than the bit lines. More rows of memory cells are, therefore, included in one steering gate line segment than are included in one bit line segment. This is done to balance the advantages of short line segments with the disadvantages of added circuit area and other overhead that is consumed by segment-select transistors, one such transistor being required for connecting each line segment to a global version of that line. Because the voltage applied to the steering gates is higher than that applied to the bit lines, in general, the select transistors for the steering gate line segments are relatively large in circuit area while those for the bit line segments may be kept relatively small. Therefore, the balance of advantages and disadvantages is different for segmenting the steering gate lines and the bit lines. As a result, the bit lines are broken into shorter segments than the steering gate lines.
According to another aspect of the present invention, a memory array, such as the second or third type identified above, also has its steering gate lines divided into segments but rather than using select transistors to connect the lines of each segment to respective global lines, every Nth steering gate of each segment is connected together, and a resulting N number of electrically separate global steering gate lines of each segment are connected directly to the steering gate decoder. The number N depends on the specific memory, typically on how close floating gate storage elements being programmed at the same time in one row may be to each other without disturbing the charge on cells in that row that are not being programmed. N=4 is an example. In this way, the relatively large steering segment select transistors are eliminated. The steering gate decoder directly drives the correct steering gate line segments without increasing the complexity of the steering gate decoder. The bit lines may be segmented with the same segment lengths as the steering gates, or may be made different. Additional aspects, features and advantages of the present invention are included in the following description of its exemplary embodiments, which description should be taken in conjunction with the accompanying drawings.